74LVC2G07 - Buffers

NXP

74LVC2G07 Datasheet Preview — Preview of 74LVC2G07 PDF

Datasheet Details

Part number	74LVC2G07
Manufacturer	NXP ↗
File Size	82.65 KB
Description	Buffers
Datasheet	74LVC2G07_PhilipsSemiconductors.pdf

74LVC2G07 Product details

Description

74LVC2G07 The 74LVC2G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families.Input can be driven from either 3.3 V or 5 V devices.This feature allows the use of this device in a mixed 3.3 V and 5 V environment.Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.This device is fully specified for partial power-down applications using Ioff.The Ioff circuitry disables the outp

Features

Wide supply voltage range from 1.65 V to 5.5 V.
5 V tolerant input/output for interfacing with 5 V logic.
High noise immunity.
Complies with JEDEC standard:.
JESD8-7 (1.65 V to 1.95 V).
JESD8-5 (2.3 V to 2.7 V).
JESD8B/JESD36 (2.7 V to 3.6 V).
24 mA output drive (VCC = 3.0 V).
CMOS low power consumption.
Latch-up performance exceeds 250 mA.
Direct interface with TTL levels.
Inpu.

📁 74LVC2G07 Similar Datasheet

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Other Datasheets by NXP

74LVC2G00-Q100 - Dual 2-input NAND gate
74LVC2G02 - Dual 2-input NOR gate
74LVC2G02-Q100 - Dual 2-input NOR gate
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Published: Mar 22, 2005 |