74VHCT08 Datasheet PDF - NXP Quad 2-input AND gate Specs

74VHCT08 - Quad 2-input AND gate

This page provides the datasheet information for the 74VHCT08, a member of the 74VHC08 Quad 2-input AND gate family.

Datasheet Summary

Description

The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are speciﬁed in compliance with JEDEC standard JESD7-A.

The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

Features

I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC08 operates with CMOS logic levels N The 74VHCT08 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from.
40 °C to +85 °C and from.
40 °C to +125 °C 3. Ordering information Table 1. Ordering information.

Datasheet Details

Part number	74VHCT08
Manufacturer	NXP
File Size	75.06 KB
Description	Quad 2-input AND gate
Datasheet	74VHCT08 Datasheet
Additional preview pages of the 74VHCT08 datasheet.

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Full PDF Text Transcription

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74VHC08; 74VHCT08 Quad 2-input AND gate Rev. 01 — 30 June 2009 Product data sheet 1. General description The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard JESD7-A. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. 2. Features I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC08 operates with CMOS logic levels N The 74VHCT08 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C 3.

Published: Aug 5, 2015 |