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LPC3250 - 16/32-bit ARM Microcontrollers

Download the LPC3250 datasheet PDF. This datasheet also covers the LPC3220 variant, as both devices belong to the same 16/32-bit arm microcontrollers family and are provided as variant models within a single manufacturer datasheet.

General Description

The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications.

Key Features

  • ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.
  • Vector Floating Point (VFP) coprocessor.
  • 32 kB instruction cache and 32 kB data cache.
  • Up to 256 kB of Internal SRAM (IRAM).
  • Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory. NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers.
  • Multi-layer AHB system that provides a separate bus for each AHB master, including both an instructio.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LPC3220_PhilipsSemiconductors.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NXP Semiconductors

Part Number Description
LPC3220 16/32-bit ARM Microcontrollers
LPC3230 16/32-bit ARM Microcontrollers
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 2.1 — 24 June 2014 Product data sheet 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU).