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P83CL882 - 80C51 Ultra Low Power ULP telephony controller

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P83CL882 Product details

Description

ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pin configuration Pin description FUNCTIONAL DESCRIPTION Oscillator circuitry The CPU Interrupt controller Port control logic Timer 0 and Timer 1 event counters Timer 2 Watchdog Timer I2C-bus serial I/O (master/slave interface) MSK modem Internal Data Memory Special Function Registers overview INSTRUCTION SET Instruction map APPLICATION INFORMATION Introduction Differences between P83CL882 and the Metalink EH emulation system The asynchronou

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