54AC273 Datasheet (National Semiconductor)

54AC273, Octal D Flip-Flop

The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

The state of each D input, one setup time before the LOW-

54AC273 Features

* n n n n n n n n n n Ideal buffer for microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous master reset See ’377 for clock enable version See ’373 for transparent latch version See ’374 for TRI-STATE ® version Outputs source/sink 24 mA ’ACT has TTL-c