54LS109 Datasheet - National Semiconductor

54LS109 Dual Positive-Edge-Triggered J-K Flip-Flops

This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs The J and K data is accepted by the flip-flop on the rising edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of.

54LS109 Features

* Y Alternate Military Aerospace device (54LS109) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6368

* 1 Order Number 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AM or DM74LS109AN See NS Pa

54LS109 Datasheet (330.29 KB)