* individual J K and set inputs and common clock and common clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as
54LS114
National Semiconductor
98.18 KB
Dual jk flip-flop.
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
June 1989
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Com.
📁 Related Datasheet
54LS11 Triple 3-Input AND Gates (National Semiconductor)
54LS10 Triple 3-Input NAND Gates (National Semiconductor)
54LS109 Dual Positive-Edge-Triggered J-K Flip-Flops (National Semiconductor)
54LS109A Dual J-K Positive-Edge-Triggered Flip-Flops (Texas Instruments)
54LS122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS (Texas Instruments)
54LS122 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS (Motorola)
54LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS (Motorola)
54LS123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS (Texas Instruments)
54LS125A QUADRUPLE BUS BUFFERS (Texas Instruments)
54LS126A QUADRUPLE BUS BUFFERS (Texas Instruments)
