Description
The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode (M) input is HIGH information present on the parallel data (P0
P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal When M is LOW data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position A HIGH signal on the Chip Select (CS) input prevents both
Features
- Y 16-bit parallel-to-serial conversion Y 16-bit serial-in serial-out Y Chip select control Y Slim 24 lead 300 mil package
Commercial 74F676PC 74F676SPC
74F676SC (Note 1)
Military
54F676DM (Note 2) 54F676SDM (Note 2) 54F676FM (Note 2) 54F676LM (Note 2)
Package Number N24A N24C J24A J24F M24B W24C E28A
Package.