ADC12DL080
Overview
The ADC12DL080 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 600 MHz Full Power Bandwidth.
- n n n n n
- Single +3.3V supply operation Internal sample-and-hold Internal or External reference Outputs 2.4V to 3.6V compatible Power down mode Duty Cycle Stabilizer Pin compatible with ADC12DL040, ADC12DL065, ADC12DL066 Key Specifications n n n n n n n
- Resolution Max Conversion Rate DNL SNR (fIN=40MHz) SNR (fIN=200MHz) SFDR (fIN=40MHz) SFDR (fIN=200MHz) Power Consumption - Operating - Power Down Mode 12 Bits 80 MSPS ± 0.4 LSB (typ) 69 d
