* n n n n n n n n Single +3.0V supply operation Internal sample-and-hold Internal reference Low power consumption Power down mode Clock and Data Frame Timing 780 Mbps serial LVDS data rate (at 65 MHz clock) LVDS serial output rated for 100 Ohm load Key Specifications n n n n n n n n Resolution DNL SN
ADC12QS065 Datasheet (725.09 KB)
ADC12QS065
National Semiconductor
725.09 KB
Quad 12-bit 65 msps a/d converter.
PRELIMINARY www.DataSheet4U.com November 2005 ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs ADC12QS065 Quad 12-Bit 65 MS.
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