CR16HCS5, CR1 Datasheet (National Semiconductor) - Family of 16-bit CAN-enabled CompactRISC Microcontrollers

CR16HCS5, CR1, Family of 16-bit CAN-enabled CompactRISC Microcontrollers

plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost.

The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.

The device contai

CR16HCS5 Features

* and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com- Block Diagram Fast Clk Slow Clk

* CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit