DM54S195 - 4-Bit Parallel Access Shift Registers
DM54S195 Features
* Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage Y Complementary outputs from last stage Y For use in high-performance accumulators processors serial-to-parallel parallel-to-seri
