74F273 Datasheet (National) - Octal D Flip-Flop

74F273, Octal D Flip-Flop

The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to

74F273 Features

* Y Y Y Y Y Y Y Y Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous Master Reset See ’F377 for clock enable version See ’F373 for transparent latch version See ’F374 for TRI-STATE version Guaranteed 4000V minimum ESD protection