74FCT273 - Octal D Flip-Flop

National

74FCT273 Datasheet Preview — Preview of 74FCT273 PDF

Datasheet Details

Part number	74FCT273
Manufacturer	National
File Size	168.48 KB
Description	Octal D Flip-Flop
Datasheet	74FCT273_NationalSemiconductor.pdf

74FCT273 Product details

Description

The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device

Features

Y Y Y Y Y Y Y Y Y Y ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is pin and functionally equivalent to IDT 54 74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing 5962-87656 Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP.

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Published: May 28, 2005 |