74FCT273 Datasheet - National

74FCT273 Octal D Flip-Flop

The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-t.

74FCT273 Features

* Y Y Y Y Y Y Y Y Y Y ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is p

74FCT273_NationalSemiconductor.pdf