MM54C165 Datasheet - National

MM54C165 Parallel-Load 8-Bit Shift Register

The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest.

MM54C165 Features

* Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility Parallel loading independent of clock Dual clock inputs Fully static operation 3V to 15V 1V 0 45 VCC (typ ) fan out of 2 driving 74L Y Y Y Connection and Block Diagrams Dual-In-Line Package

MM54C165_NationalSemiconductor.pdf