MC100EP35 Datasheet - ON Semiconductor

MC100EP35 JK Flip-Flop

The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activate.

MC100EP35 Features

* 410 ps Propagation Delay

* Maximum Frequency > 3 GHz Typical

* PECL Mode Operating Range:

* VCC = 3.0 V to 5.5 V with VEE = 0 V

* NECL Mode Operating Range:

* VCC = 0 V with VEE =

* 3.0 V to

* 5.5 V

* Open Input Default State

MC100EP35_ONSemiconductor.pdf