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MC100EP809 Differential HSTL/PECL to HSTL Clock Driver

MC100EP809 Description

3.3 V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable MC100EP809 .
The MC100EP809 is a low skew 2:1:9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input mult.

MC100EP809 Features

* 100 ps Typical Device
* to
* Device Skew
* 15 ps Typical within Device Skew
* HSTL Compatible Outputs Drive 50 W to GND with no Offset Voltage
* Maximum Frequency > 750 MHz
* 850 ps Typical Propagation Delay
* Fully Compatible with Micrel

MC100EP809 Applications

* which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a

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Differential HSTL PECL HSTL Clock Driver ON Semiconductor
ON Semiconductor MC100EP809-like datasheet