MC14526B Datasheet - ON Semiconductor

MC14526B Presettable 4-Bit Down Counters

Preset Enable (Pin 3) * If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3. Inhibit (Pin 4) * A high level on the Inhibit input pre * vents the Clock from decrementing the counter. With Cl.

MC14526B Presettable 4-Bit Down Counters The MC14526B binary counter is constructed with MOS P channel and N channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded “0” state output for divide by N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide by N operation with no a.

MC14526B Features

* 50% 10% tTLH tTHL tPLH tf VDD INHIBIT VSS tf 90% 50% 10% tw 1/fmax tPHL tr VDD VSS Figure 5. Figure 6. tw VDD RESET tr ANY P 90% 50% 10% tPLH tPHL trem ANY Q 50% VDD CLOCK 50% VSS tf VDD VSS ANY Q 50% VSS tPHL 50% Figure 7. Figure 8. VALID tr PRESET ENABLE 90% 50% 10% tPHL tPLH PRESET ENABLE

MC14526B Datasheet (108.84 KB)