SCV8163 - Ultra-Low Noise and High PSRR LDO Regulator
Pin No.
Pin Name Description 4 IN Input voltage supply pin 1 OUT Regulated output voltage.
The output should be bypassed with small 1 mF ceramic capacitor.
3 EN Chip enable: Applying VEN < 0.4 V disables the regulator, Pulling VEN > 1.0 V enables the LDO.
2 GND Common ground connection
DATA SHEET www.onsemi.com 250 mA, Ultra-Low Noise and High PSRR LDO Regulator for RF and Analog Circuits SCV8163 The SCV8163 is a next generation of high PSRR, ultra low noise LDO capable of supplying 250 mA output current.
Designed to meet the requirements of RF and sensitive analog circuits, the SCV8163 device provides ultra low noise, high PSRR and low quiescent current.
The device also offer excellent load/line transients.
The SCV8163 is designed to work with a 1 mF input an
SCV8163 Features
* Operating Input Voltage Range: 2.2 V to 5.5 V
* Available in Fixed Voltage Option: 1.2 V to 5.3 V
* ±2% Accuracy Over Load/Temperature
* Ultra Low Quiescent Current Typ. 12 mA
* Standby Current: Typ. 0.1 mA
* Very Low Dropout: 80 mV at 250 mA @ 3.3 V
