SN74LS76A
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Dual jk flip-flop.
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SN74LS76A - DUAL J-K FLIP-FLOPS
(Texas Instruments)
SN5476, SN54LS76A
SN7476, SN74LS76A
DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR
SDLS121 – DECEMBER 1983 – REVISED MARCH 1988
PRODUCTION DATA informatio.
SN74LS76A - Dual JK Filp-Flop
(Motorola)
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SN74LS724 - Voltage Controlled Oscillator
(Motorola Semiconductor)
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SN74LS73A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
(Motorola)
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so .
SN74LS73A - DUAL J-K FLIP-FLOPS
(Texas Instruments)
SN5473, SN54LS73A, SN7473, SN74LS73A DUAL J-K FLIP-FLOPS WITH CLEAR
SDLS118 – DECEMBER 1983 – REVISED MARCH 1988
PRODUCTION DATA information is curre.
SN74LS748 - 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
(Motorola)
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decodi.
SN74LS74A - Dual D-Type Positive Edge-Triggered Flip-Flop
(ON Semiconductor)
SN74LS74A
Dual D−Type Positive Edge−Triggered Flip−Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
SN74LS74A - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
(Motorola)
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D.
SN74LS74A - Dual D-Type Positive-Edge Triggered Flip-Flops
(Texas Instruments)
SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR
SDLS119 − DECEMBER 1983 − R.
SN74LS75 - 4-BIT D LATCH LOW POWER SCHOTTKY
(Motorola)
4-BIT D LATCH
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and in.
