82C283 Datasheet (Opti) - 386SX System Controller

82C283, 386SX System Controller

Clock and Reset Interface Signals Pin No.

43 22 104 18 Signal Type I I/O O I Signal Description CLK2 input from oscillator.

CLK2 output to 386SX and 387SX.

(Bidirectional output is always enabled.) 1.19MHz output.

14.31818MHz oscillator input.

Signal Name CLKI PCLK2 OSC12 OSC 3.1.2 CPU Control a

82C283 Features

* 2.0 Overview

* Flexible DRAM banks configuration - Supports 256K, 1M and 4M DRAM

* Block interleave mode operations - Block interleaving at a block size of 512 bytes

* BIOS shadow RAM - Shadow RAM for system, video and adapter BIOS

* Memory remapping

* Flex