82C283 - 386SX System Controller

82C283 Datasheet Preview — Preview of 82C283 PDF

Datasheet Details

Part number	82C283
Manufacturer	Opti
File Size	242.25 KB
Description	386SX System Controller
Datasheet	82C283_Opti.pdf

82C283 Product details

Description

Clock and Reset Interface Signals Pin No.43 22 104 18 Signal Type I I/O O I Signal Description CLK2 input from oscillator.CLK2 output to 386SX and 387SX.(Bidirectional output is always enabled.) 1.19MHz output.14.31818MHz oscillator input.Signal Name CLKI PCLK2 OSC12 OSC 3.1.2 CPU Control and Interface Signals Pin No.67:61 60:52 Signal Type I I/O Signal Description CPU Address Bus: Address lines 23 through 17 and 7 through 0. CPU Address Bus: Address lines 16 through 8. These signals a

Features

2.0 Overview.
Flexible DRAM banks configuration - Supports 256K, 1M and 4M DRAM.
Block interleave mode operations - Block interleaving at a block size of 512 bytes.
BIOS shadow RAM - Shadow RAM for system, video and adapter BIOS.
Memory remapping.
Flexible multiplexed DRAM address.
Programmable AT bus clock.
Turbo switch.
160-pin PQFP (Plastic Quad Flat Pack) The 82C283 is a highly integrated, AT system logic VLSI chip f.

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Published: Nov 5, 2007 |