Click to expand full text
PI6CU877
PLL Clock Driver for 1.8V DDR2 Memory
Features
• PLL clock distribution optimized for DDR2 SDRAM applications. • Distributes one differential clock input pair to ten differential clock output pairs. • Differential www.DataSheet4U.com Inputs (CLK, CLK) and (FBIN, FBIN) • Input OE/OS: LVCMOS • Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers • Packaging (Pb-free & Green available): – 52-ball VFBGA (NF)
Description
PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels.