* section in the introduction Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits[3:2] offset 48h
* Extended Chip Control Register (section 14.1.31) Corrected configuration register offset 80h (bit[15:0]
PI7C8150B
Pericom Semiconductor Corporation
2.75 MB
Asynchronous 2-port pci-to-pci bridge.
www.DataSheet4U.com
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE REVISION 2.02
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