* Master/Slave clock selection in a backplane application 160 MHz operation (typical) 100ps duty cycle distortion (typical) 50ps channel to channel skew (typical) 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design (16mA @ 3.3V static) Accepts small swing
PI90LVB16 Datasheet (462.10 KB)
PI90LVB16
Pericom Semiconductor
462.10 KB
3v bus lvds 1-to-6 clock buffer/bus transceiver.
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