* Line Time Generation (From 9 Stage Clock Driven Counter)
* Line Timing, Frame Alignment
* Alarm Signals FAT + MIR, ATL, AW, EPAT
* Test Points TP1, TP2, TP3, MR
* Inputs and Outputs LSTTL Compatible OG24 Fig. 1 Pin connections (top view) ,
MJ1472
Plessey
101.75 KB
Pcm receiving.
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MJ1472
A_DV_A_N_C_E_IN_F_OR_M_A_T_IO_N
Advance information is issued to advise Customers of new additions to the Plessey Semicon.
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