MJ1472 Datasheet (Plessey)

MJ1472, PCM RECEIVING

e ________ !:~!!!!! MJ1472 A_DV_A_N_C_E_IN_F_OR_M_A_T_IO_N Advance information is issued to advise Customers of new additions to the Plessey Semiconductors range which, nevertheless, still have 'pre-production' status.

Details given may, therefore, change without notice although we would expect this performance data to be representative of 'full production' status product in most cases.

Please contact your local Plessey Semiconductors Sales Office for details of current status.

MJ1472 PCM RE

MJ1472 Features

* Line Time Generation (From 9 Stage Clock Driven Counter)

* Line Timing, Frame Alignment

* Alarm Signals FAT + MIR, ATL, AW, EPAT

* Test Points TP1, TP2, TP3, MR

* Inputs and Outputs LSTTL Compatible OG24 Fig. 1 Pin connections (top view) ,