HYB18T256400BC Datasheet - Qimonda

HYB18T256400BC 256-Mbit Double-Data-Rate-Two SDRAM

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchrono.

July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History: 2007-07, Rev. 1.11 Page All All Subjects (major changes since last revision) A.

HYB18T256400BC Features

* The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality

* DRAM organizations with 4, 8 a

HYB18T256400BC Datasheet (4.11 MB)