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HYB18T256400BC

256-Mbit Double-Data-Rate-Two SDRAM

HYB18T256400BC Features

* The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:

* Off-Chip-Driver impedance adjustment (OCD) and

* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality

* DRAM organizations with 4, 8 a

HYB18T256400BC General Description

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchrono.

HYB18T256400BC Datasheet (4.11 MB)

Preview of HYB18T256400BC PDF

Datasheet Details

Part number:

HYB18T256400BC

Manufacturer:

Qimonda

File Size:

4.11 MB

Description:

256-mbit double-data-rate-two sdram.
July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 .

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Da ta Sh e et , V 0. 2 2, Fe b. 2 00 4 H YS72 T 320 00 GR (2 56 M B y t e ) H YS72 T 640 01 GR (5 12 M B y t e ) H YS72 T 640 20 GR (5 12 M B y t e ).

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HYB18T256400BC 256-Mbit Double-Data-Rate-Two SDRAM Qimonda

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