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HYI18T1G800B - 1-Gbit Double-Data-Rate-Two SDRAM

This page provides the datasheet information for the HYI18T1G800B, a member of the HYI18T1G160B 1-Gbit Double-Data-Rate-Two SDRAM family.

Datasheet Summary

Description

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

Features

  • The 1-Gbit Double-data-Rate SDRAM offers the following key features:.
  • Off-Chip-Driver impedance adjustment (OCD) and On.
  • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.
  • DRAM organizations with 4, 8 and 16 data in/outputs.
  • Auto-Precharge operation for read and write bursts.
  • Double Data Rate architecture: two data transfers per.
  • Auto-Refresh, Self-Refresh and power saving Powerc.

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Datasheet preview – HYI18T1G800B

Datasheet Details

Part number HYI18T1G800B
Manufacturer Qimonda
File Size 4.06 MB
Description 1-Gbit Double-Data-Rate-Two SDRAM
Datasheet download datasheet HYI18T1G800B Datasheet
Additional preview pages of the HYI18T1G800B datasheet.

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Full PDF Text Transcription

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July 2007 HY[B/I]18T1G400B[F/C](L) HY[B/I]18T1G800B[F/C](L) HY[B/I]18T1G16[0/7]B[F/C](L/V) www.DataSheet4U.com 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.3 Internet Data Sheet HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM HY[B/I]18T1G400B[F/C](L), HY[B/I]18T1G16[0/7]B[F/C](L/V), HY[B/I]18T1G800B[F/C](L) Revision History: 2007-07, Rev. 1.3 Page All www.DataSheet4U.com Subjects (major changes since last revision) Adapted internet edition Added PG-TFBGA-92 HYB18T1G167BF-3.7, HYB18T1G167BF-3S, HYB18T1G167BF-3, HYB18T1G167BF-2.5, HYB18T1G167BF-25F, HYB18T1G160BFV-3.7, HYB18T1G160BFV-3S Previous Revision: 2007-05, Rev. 1.
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