* Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustme
HYS72T512341HJP-5-B Datasheet (1.72 MB)
HYS72T512341HJP-5-B
Qimonda
1.72 MB
240-pin registered ddr2 sdram modules.
December 2006
www.DataSheet4U.com
HYS72T512341HHP
*[3.7/5]
*B HYS72T512341HJP
*[3.7/5]
*B HYS72T512341HKP
*[3.7/5].
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