HYS72T64301HP-3S-A Datasheet PDF - Qimonda 240-Pin Registered DDR2 SDRAM Modules Specs

HYS72T64301HP-3S-A - 240-Pin Registered DDR2 SDRAM Modules

Datasheet Summary

Description

capacitive loading to the system bus, but adds one cycle to the SDRAM timing.

Decoupling capacitors are mounted on the PCB board.

The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol.

Features

Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type.
Auto Refresh (CBR) and Self Refresh.
Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9 µs between 85 °C and 95 °C.
Programmable self refresh rate via EMRS2 setting.
All inputs and outputs SSTL_18 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT).
Serial Presence Detect with E2PROM.
Based on standard re.

Datasheet Details

Part number	HYS72T64301HP-3S-A
Manufacturer	Qimonda
File Size	2.32 MB
Description	240-Pin Registered DDR2 SDRAM Modules
Datasheet	HYS72T64301HP-3S-A Datasheet
Additional preview pages of the HYS72T64301HP-3S-A datasheet.

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Full PDF Text Transcription

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October 2006 www.DataSheet4U.com HYS72T64301HP–[3S/3.7]–A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Compliant Internet Data Sheet Rev. 1.0 Internet Data Sheet www.DataSheet4U.com HYS72T64301HP–[3S/3.7]–A Registered DDR2 SDRAM Modules HYS72T64301HP–[3S/3.7]–A Revision History: 2006-10, Rev. 1.0 Page All All Subjects (major changes since last revision) Adapted internet edition Initial document We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.

Published: May 1, 2010 |