V7001 - SDR-SDRAM Memory Controller

V7001 Datasheet Preview — Preview of V7001 PDF

Datasheet Details

Part number	V7001
Manufacturer	Qualcore
File Size	67.03 KB
Description	SDR-SDRAM Memory Controller
Datasheet	V7001_Qualcore.pdf

V7001 Product details

Description

Document Self checking Verification Suite Synthesis Scripts Scripts for STA & DFT (optional) QCL_10208_DF_02_Datasheet_rev101 QualCore Logic, Inc.1289, ANVILWOOD AVENUE SUNNYVALE, CA - 94089, USA Tel: 408 541 0730 Fax: 408 541 0740 E-mail: sales@qualcorelogic.com http://www.qualcorelogic.com

Features

JEDEC standard SDR-SDRAM supported.
Transaction pipeline for maximum utilization of the Memory Bus.
3 Request buffers for transaction pipeline.
Supports CAS latencies of 1, 2 and 3.
4 or 8 beat burst transactions supported.
Supports up to 4 chip selects of Memory devices.
Page mode support for up to 16 open pages.
Supports flexible Row and Column addressing.
Supports up to 4GB of Memory Address space.
Supp.

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Published: Mar 6, 2008 |