V7001 Datasheet (Qualcore) - SDR-SDRAM Memory Controller

V7001, SDR-SDRAM Memory Controller

Document * Self checking Verification Suite * Synthesis Scripts * Scripts for STA & DFT (optional) QCL_10208_DF_02_Datasheet_rev101 QualCore Logic, Inc.

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V7001 Features

* JEDEC standard SDR-SDRAM supported

* Transaction pipeline for maximum utilization of the Memory Bus

* 3 Request buffers for transaction pipeline

* Supports CAS latencies of 1, 2 and 3

* 4 or 8 beat burst transactions supported

* Supports up to 4 chip