V7001 SDR-SDRAM Memory Controller

Description

www.DataSheet4U.com V7001 SDR-SDRAM Memory Controller .
Document. Self checking Verification Suite. Synthesis Scripts. Scripts for STA & DFT (optional) QCL_10208_DF_02_Datasheet_.

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Datasheet Specifications

Part number: V7001
Manufacturer: Qualcore
File Size: 67.03 KB
Datasheet: V7001_Qualcore.pdf
Description: SDR-SDRAM Memory Controller

Features

* JEDEC standard SDR-SDRAM supported
* Transaction pipeline for maximum utilization of the Memory Bus
* 3 Request buffers for transaction pipeline
* Supports CAS latencies of 1, 2 and 3
* 4 or 8 beat burst transactions supported
* Supports up to 4 chip

Applications

* Can be easily interfaced to any SoC designs that need to interact with SDR-SDRAM
* In embedded memory intensive applications Test Coverage
* Design is highly synchronous and scan friendly
* Fault coverage is 94% with ATPG vectors Deliverables
* Fully synth

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V7001 SDR-SDRAM Memory Controller Qualcore

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