V360EPC Datasheet - QuickLogic

V360EPC Local Bus to PCI Bridge

and Pinout Table 2 below lists the pin types found on the V360EPC. Table 3 describes the function of each pin on the V360EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package. Table 2: Pin T.

Glueless interface to i960Cx/Hx and AMD29030/40 processors Configurable for primary master, bus master or target operation. Type 0 and type 1 configuration cycles. Up to 1Kbyte burst access on PCI or local. Large, 640-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture 64-byte read FIFO per aperture. Enhanced support for 8/16-bit local bus devices with programmable region sizes. 3.3 volt suppor.

V360EPC Features

* like Hot Swap and DMA chaining. The PCI bus can be run at full 33MHz, independent of local bus clock rate. The overall throughput of the system is dramatically improved by increasing the FIFO m o .c U 4 t e e h S a t a m .D o .c w U 4 t w e e w h aS

* Hot swapping capability

* 16 8-

V360EPC_QuickLogic.pdf