R1100
Features
CPU Core
- RDC’s proprietary RISC architecture
- Five-stages pipeline
- Operation frequency: 80MHz
- Support CPU ID
- Supports 32 PIO pins
- External bus, Internal bus and core in the same clock base l l l l Interrupt Controller
- The interrupt controller with seven maskable external interrupts and one non-maskable external interrupt (NMI) Two Independent DMA Channels Integrate PLL(- 1~- 8) Programmable Chip-select Logic
- Programmable chip-select logic for Memory or I/O bus cycle decoder l l Programmable Wait-state Generator Counter/Timers
- Three independent 16-bit timers and one independent programmable watchdog timer l Operating Voltage Range
- Operation voltage: 3.3V
- I/O pin input voltage: 3.3V ~ 5V patible with generic 80C186 l
- I/O pin output voltage: 3.3V Package Type
- 100 Pin PQFP & LQFP l A Green Product l
Bus interface
- Multiplexed address and Data bus
- With 8-bit or 16-bit boot ROM bus size
- Supports direct address bus [A19 : A0]
- 8-bit or 16-bit external...
