524S Datasheet (Renesas) - Low Skew 1 to 4 Clock Buffer

524S, Low Skew 1 to 4 Clock Buffer

The 524S is a low skew, single input to four output, clock buffer.

The 524S has best in class additive phase jitter of sub 50 fsec.

The 524S is Power Down Tolerant (PDT).

PDT designated inputs may be driven before VDD is applied, without damage to the device.

Renesas makes many non-PLL and PLL based

524S Features

* Low additive phase jitter RMS: 50fs

* Extremely low skew outputs (50ps)

* Low cost clock buffer

* Packaged in 8-SOIC and 8-DFN, Pb-free

* ICLK is PDT and may be driven before VDD is applied

* Direct-coupled signal path suitable for 1pps clocks