873996 Datasheet - Renesas

873996 Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receiv.

873996 Features

* Six differential 3.3V LVPECL outputs

* Selectable differential clock inputs

* CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

* Input clock frequency range: 49MHz to 213.33MHz

* Output clock frequency ran

873996-Renesas.pdf