8A34001 - SMU

Renesas

Datasheet Details

Eight independent timing channels.
Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO) or Digital Phase Lock Loop (DPLL).
DPLLs generate telecom compliant clocks.
Compliant with ITU-T G.8262 for Synchronous Ethernet.
Compliant with legacy SONET/SDH and PDH requirements.
DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 12µHz to 22kHz.
DPLL/DCO channels share frequency i.

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Published: Aug 16, 2023 |