8A34001 Datasheet - Renesas

8A34001 SMU

Synchronization Management Unit 8A34001 Datasheet Overview The 8A34001 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). Optional clock recovery filter/servo software is available under license from Renesas for .

8A34001 Features

* ▪ Eight independent timing channels

* Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO) or Digital Phase Lock Loop (DPLL)

* DPLLs generate telecom compliant clocks ▪ Compliant with ITU-T G.8262 for Synchronous Ethernet ▪ Compliant with

8A34001 Datasheet (2.52 MB)