9ZML1253E, 9ZML1233E Datasheet - Renesas

9ZML1253E, 9ZML1233E, 2:12 DB1200ZL Derivative

2:12 DB1200ZL Derivative for PCIe Gen1-4 and UPI 9ZML1233E/9ZML1253E Datasheet Description The 9ZML1233E/9ZML1253E are second generation enhanced pe

Features

* ▪ 12 Low-Power (LP) HCSL output pairs (1233E) ▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E) Block Diagram Features ▪ SMBus write lock feature; increases system security ▪ 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies ▪ LP-HCSL outpu

Applications

* while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1233E and 9ZML1253E have an SMBus Write Lockout pin for increased device and system security. PCIe Clocking Architectures ▪ Common Clocked (C

9ZML1233E-Renesas.pdf