Overview: CD4017BMS, CD4022BMS
CMOS Counter/Dividers CD4017BMS - Decade Counter with 10 Decoded Outputs CD4022BMS - Octal Counter with 8 Decoded Outputs CD4017BMS and CD4022BMS are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high speed operation, 2-input decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counter sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRYOUT signal completes one cycle every 10 clock input cycles in the CD4017BMS or every 8 clock input cycles in the CD4022BMS and is used to ripple-clock the succeeding device in a multi-device counting chain. The CD4017BMS and CD4022BMS series types are supplied in these 16 lead outline packages Braze Seal DIP *H4W †H4X Frit Seal DIP *H1F †H1E Ceramic Flatpack H6W *CD4017B Only † CD4022B Only Functional Diagrams
CD4017BMS CLOCK CLOCK INHIBIT
RESET
VCC = 16 VSS = 8 14 3 “0” 13 2 “1” 15 4 “2”
7 “3” DECODED 10 “4” DECIMAL
1 “5” OUT 5 “6” 6 “7” 9 “8” 11 “9” 12 CARRY OUT CD4022BMS CLOCK CLOCK INHIBIT
RESET 14 13 15 VCC = 16 VSS = 8 2 “0” 1 “1” 3 7 11 “2” “3” DECODED “4” OUT 4 “5” 5 “6” 10 “7” 12 CARRY OUT FN3297 Rev 0.00 August 1998 DATASHEET FN3297 Rev 0.
