CSPT855 Datasheet - Renesas

CSPT855 2.5V PHASE LOCKED LOOP CLOCK DRIVER

The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in.

CSPT855 Features

* PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications

* Spread spectrum clock compatible

* Operating frequency: 60MHz to 220MHz

* Low jitter (cycle-to-cycle): ±50ps

* Distributes one differential clock input to four differential clock ou

CSPT855-Renesas.pdf