IDT71V124SA Datasheet | Renesas

Features - 128K x 8 advanced high-speed CMOS static RAM - JEDEC revolutionary pinout (center power/GND) for reduced noise - Equal access and cycle times - mercial: 10/12/15ns - Industrial: 12/15ns - One Chip Select plus one Output Enable pin - Inputs and outputs are LVTTL-patible - Single 3.3V supply - Low power consumption via chip deselect - Available in a 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages. Description The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, bined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-patible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Functional Block Diagram A0 - - - A16 ADDRESS DECODER - - - 1,048,576-BIT MEMORY ARRAY I/O0 - I/O7 8 8 WE OE CONTROL CS LOGIC I/O CONTROL . 3873 drw 01 © 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2013 DSC-3873/11 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout mercial and Industrial Temperature Ranges Pin Configuration A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6...