R5F51101AGFL Renesas Datasheet

R5F51101AGFL Key Features

• 32-bit RX CPU core
• 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz
• Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations
• Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycl
• Fast interrupt
• CISC Harvard architecture with five-stage pipeline
• Variable-length instruction format, ultra-pact code
• On-chip debugging circuit
• Low power consumption functions
• Operation from a single 1.8 to 3.6 V supply