R5F562T7EDFH Datasheet | Renesas

Features - 32-bit RX CPU core - Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz - Single precision 32-bit IEEE-754 floating point - Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations - Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle) - Fast interrupt - Divider (fastest instruction execution takes two CPU clock cycles) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions: Ultra-pact code - Supports the memory protection unit (MPU) - Background JTAG debugging plus high-speed tracing - Operating voltage - Single 3.3- or 5-V supply; 5-V analog supply is possible with 3.3-V products - Low-power design and architecture - Four low-power modes - On-chip main flash memory, no wait states - 100-MHz operation, 10-ns read cycle - No wait states for reading at full CPU speed - 64-Kbyte/128-Kbyte/256-Kbyte capacities - For instructions and operands - User code programmable via the SCI or JTAG - On-chip data flash memory - Max. 32 Kbytes, reprogrammable up to 30,000 times - Erasing and programming impose no load on the CPU. - On-chip SRAM, no wait states - 8-Kbyte/16-Kbyte SRAM - For instructions and operands - DMA - DTC: The single unit is capable of transfer on multiple channels - Reset and supply management - Power-on reset (POR) - Low voltage detection (LVD) with voltage settings - Clock functions - External crystal oscillator or internal PLL for operation at 8 to 12.5 MHz - Internal 125-k Hz LOCO for the IWDT - Detection of main oscillator stoppage (for IEC 60730 pliance) - Independent watchdog timer (for IEC60730pliance) - 125-k Hz LOCO clock...