R5F563NBDDLC Datasheet - Renesas

100-MHz 32-bit RX MCU

R5F563NBDDLC Features

* RX63N Group, RX631 Group Renesas MCUs R01DS0098EJ0180 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various communications interfaces including Ethernet MAC, Rev.1.80 May 13, 2014 full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D converters, RTC

R5F563NBDDLC General Description

* Maximum operating frequency: 100 MHz * 32-bit RX CPU * Minimum instruction execution time: One instruction per state (cycle of the system clock) * Address space: 4-Gbyte linear * Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Ac.

R5F563NBDDLC Datasheet (1.50 MB)