* of the memory device are summarized in Table 3. The hardware write protection, controlled by the W pin, restricts write access to the Status Register (though not to the WIP and WEL bits, which are set or reset by the device internal logic). Bit 7 of the status register (as shown in Table 5) is the
M95128
174.59 KB
256/128 kbit serial spi bus eeprom with high speed clock.
M95256 M95128
256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
PRELIMINARY DATA
s s s s
SPI Bus Compatible Serial Interface Supports Positive.
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