10F269-T3 Datasheet - STMicroelectronics

10F269-T3 ST10F269-T3

MEMORY ORGANIZATION INTERNAL FLASH MEMORY OVERVIEW OPERATIONAL OVERVIEW ARCHITECTURAL DESCRIPTION Read Mode Command Mode Ready/Busy Signal Flash Status Register Flash Protection Register Instructions Description Reset Processing and Initial State FLASH MEMORY CONFIGURATION APPLICATION .

ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM HIGH PERFORMANCE 32MHz CPU WITH DSP FUNCTION 16-BIT CPU WITH 4-STAGE PIPELINE 62.5ns INSTRUCTION CYCLE TIME AT 32MHz www.DataSheet4U.com MAX CPU CLOCK MULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT MULTIPLICATION, 40-BIT ACCUMULATOR REPEAT UNIT ENHANCED BOOLEAN BIT MANIPULATION FACILITIES ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS SINGL.

10F269-T3 Features

* Enhanced Addressing Capabilities Multiply-Accumulate Unit Program Control INSTRUCTION SET SUMMARY MAC COPROCESSOR SPECIFIC INSTRUCTIONS EXTERNAL BUS CONTROLLER PROGRAMMABLE CHIP SELECT TIMING CONTROL READY PROGRAMMABLE POLARITY 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.4 5.5

10F269-T3 Datasheet (1.24 MB)