ST10F269Z2T3 Datasheet - STMicroelectronics

ST10F269Z2T3 16-BIT MCU

13 4 - Memory Organization 14 5 - Internal Flash Memory 17 5.1 - OVERVIEW 17 5.2 - OPERATIONAL OVERVIEW 17 5.3 - ARCHITECTURAL DESCRIPTION 19 5.3.1 - Read Mode 19 5.3.2 - Command Mode 19 5.3.3 - Ready/Busy Signal 19 5.3.4 - Flash Status Register 19 5.3.5 - Flash Protection Register 21.

ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET HIGH PERFORMANCE 32 OR 40 MHZ CPU WITH DSP FUNCTION 16-bit CPU With 4-stage Pipeline 50ns (or 62.5ns) Instruction Cycle Time at 40MHz (or 32MHz) Max CPU Clock Multiply/accumulate Unit (Mac) 16 X 16-bit Multiplication, 40-bit Accumulator Repeat Unit Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and.

ST10F269Z2T3 Features

* 37 6.1.1.1 -Enhanced Addressing Capabilities 37 6.1.1.2 -Multiply-Accumulate Unit 37 6.1.1.3 -Program Control 37 6.2 - INSTRUCTION SET SUMMARY 38 6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS 39 7 - External Bus Controller 43 7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL 43 7.2 - READY PROGR

ST10F269Z2T3 Datasheet (1.58 MB)