KM44S32030B Datasheet - Samsung semiconductor

KM44S32030B 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

The KM44S32030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock.

KM44S32030B CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 1999 KM44S32030B Revision History Revision 0.0 (May 15, 1999) CMOS SDRAM Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. Skip ICC4 value of CL=2 in DC characteristics in datasheet. Define a new parameter of tDAL( 2CLK +20ns), Last data in.

KM44S32030B Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 Page ) -. Burst type (Sequential & Interleave)

* All inputs are sampl

KM44S32030B_Samsungsemiconductor.pdf