LH6V4256 Datasheet - Sharp Electrionic Components

LH6V4256 CMOS 1M (256K x 4) Dynamic RAM

The LH6V4256 is a 262,144 word × 4-bit dynamic RAM which allows fast page mode access. The LH6V4256 is fabricated on SHARP’s advanced CMOS double-level polysilicon gate technology. With its input multiplexed and packaged in the standard 20-pin DIP, 26-pin SOJ, or 28-pin TSOP (I) packages, it is easy.

LH6V4256 FUNCTION 262,144 words × 4 bit Access time: 100 ns (MAX) Cycle time: 190 ns (MIN) Fast page mode cycle time: 60 ns (MIN) Power supply: +3.3 V ±0.3 V Power consumption (MAX): Operating: 126 mW Standby: 0.54 mW Built-in latch circuit for row-address, column-address, and input data OE = Don’t care in early write operation RAS only refresh, hidden refresh, and CAS before RAS refresh capability .

LH6V4256 Features

* COLUMN ADDRESS tCWS tRWL tWP WE VIH VIL tOEH VIH VIL tOED tOEZ VIH VIL tDS tDH O

LH6V4256 Datasheet (198.73 KB)