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256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
• High Performance: -8 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns • Multiple Burst Read with Single Write Operation • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (× 4, × 8) • Data Mask for byte control (× 16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • 8192 refresh cycles/64 ms 7,8 µ • Random Column Address every CLK (1-N Rule) • Single 3.3 V ± 0.3 V Power Supply • LVTTL Interface versions • Plastic Packages: P-TSOPII-54 400mil width (× 4, × 8, × 16) • -8 part for PC100 2-2-2 operation -8B part for PC100 3-2-3 operation -10 part for PC66 2-2-2 operation
fCK tCK3 tAC3 tCK2 tAC2
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HYB39S256400T Datasheet
