SI53325 Datasheet (Silicon Laboratories) - Low-Jitter LVPECL Fanout Clock Buffers

SI53325, Low-Jitter LVPECL Fanout Clock Buffers

Functional Description The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers.

All devices except the Si53326 and Si53328 have a universal input that accepts most common differential or LVCMOS input signals.

The Si53326 and Si53328 accept only single-ended LVCMOS input

SI53325 Features

* include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance. KEY FEATURES

* Ultra-low additive jitter: 50 fs rms

* Built-in LDOs for high PSRR performance