Description
TTL power surpply , should be connected to 3.3V ± 5% TTL ground, connected to 0V Logical core power surpply, connected to 3.3V ± 5% Logical core ground, connected to 0V Analog power surpply, connected to 3.3V ± 5% Analog ground, connected to 0V Analog substrate, connected to 0V
Digital Signals Pin Name SFTCLK RED1 (5 to 0) GRN1 (5 to 0) BLU1 (5 to 0) RED0 (5 to 0) GRN0 (5 to 0) BLU0 (5 to 0) HSYNC VSYNC CNTL (3 to 0) PANEL (1, 0) CKMODE LOS SDATAP/N REFRQP/N 72 14, 15, 16, 17, 18, 19 6, 7, 8,
Features
- 1 chip receiver for serial transmission of 18bit color VGA/SVGA/XGA picture.
- On chip differential cable driver.
- TTL/CMOS compatible interface.
- Support 1 pixel/shiftclock mode & 2 pixel/shiftclock mode.
- +3.3V single power supply.
- Low power consumption.
- 80pin Plastic QFP Package (Body size: 14mm × 14mm) Block Digagram & Pin out
LPFB LPFA VCCA VEEA VEES
80 pin QFP (Plastic)
REFRQN
REFRQP
RED0 (0)
RED0 (1)
RED0 (2)
RED0 (3)
RED0.
CXB1452Q_SonyCorporation.pdf
